1. Field of the Invention
The present invention relates to semiconductor circuit devices and more specifically to a semiconductor circuit device having active and standby states.
2. Description of the Background Art
Prior Art 1
In miniaturizing transistors, power supply voltage is not always scaled down in accordance with the scale-down of a device but power supply voltage may remain constant when a device size is reduced. In this case, electric field strength in the vicinity of a drain increases. Accordingly, hot carriers are generated in a channel and injected into a gate oxide film, thereby deteriorating the characteristics of a transistor element. One method of solving this problem is called NOEMI (Normally-On Enhancement MOSFET Insertion). FIG. 40 shows one example of NOEMI. In this example, an N channel MOS transistor Qn2 is provided between the drain terminal of an N channel MOS transistor Qn1 and the output node of an inverter formed of a P channel MOS transistor Qp1 and N channel MOS transistor Qn1. Since the voltage of Vcc is always applied to the gate of N channel MOS transistor Qn2, N channel MOS transistor Qn2 is always in the on state. By thus providing N channel MOS transistor Qn2, the drain voltage of N channel MOS transistor Qn1 is limited to (gate voltage of N channel MOS transistor Qn2)xe2x88x92(threshold of N channel MOS transistor Qn2).
In a CMOS type semiconductor device, in accordance with miniaturization of a device, power supply voltage is decreased so as to ensure the reliability of the device and reduce power consumption. In order to achieve high speed operation in this situation, the threshold of each MOS transistor needs to be lowered in accordance with the decreased power supply voltage. In this case, a subthreshold current flowing between a source and a drain when a transistor is in the off state increases. This increases a direct current in the entire large scale integration and especially increases a standby current in a dynamic semiconductor memory device. One method of solving this problem is the MT-CMOS (Multi-Threshold CMOS) configuration. One example of the MT-CMOS configuration will be described with reference to FIG. 41. An N channel MOS transistor Qn11 having a threshold (Mid-Vth) higher than that of a transistor in a CMOS inverter C1 is provided in series with inverter C1 operating at a low threshold. By controlling a control signal xcfx86 so that N channel MOS transistor Qn11 is turned on in an active state and turned off in a standby state, inverter C1 operates at high speed in the active state and the subthreshold current is decreased in the standby state.
Prior Art 2
One method capable of achieving the same effect as the MT-CMOS is to decrease a subthreshold current by causing the gate potential of N channel MOS transistor Qn11 shown in FIG. 41 to be a minus potential in the standby state.
Prior Art 3
In typical memory LSIs and logic LSIs, most node voltages are often predetermined in the standby state. As described in Very Large Scale Integration Memory, (1994), Baifukan S1, p. 365, there is a method to decrease a subthreshold current in the standby state by a logic circuit having a hierarchical configuration of power supplies. FIG. 42 is a block diagram showing one example of the logic circuit structure. The logic circuit includes an inverter IVL connected between a main power supply line MVcc and a sub ground line subGND and receiving an L level input signal in the standby state, an inverter IVH connected between a sub power supply line subVcc and a main ground line MGND and receiving an H level input signal in the standby state, a P channel MOS transistor Qp21 connected between main power supply line MVcc and sub power supply line subVcc and turned on/off in response to a control signal/xcfx86, and an N channel MOS transistor Qn21 connected between main ground line MGND and sub ground line subGND and turned on/off in response to a control signal xcfx86. Control signal xcfx86 is at the L level in the standby state and at the H level in the active state.
The thus structured logic circuit has its P channel MOS transistor Qp21 and N channel MOS transistor Qn21 turned off in the standby state. Accordingly, a subthreshold current flowing between the output node of inverter IVL and sub ground line subGND and a subthrreshold current flowing between the output node of inverter IVH and sub power supply line subVcc are decreased. In the active state, Qp21 and Qn21 are on and the logic circuit performs a normal operation.
Prior Art 4
As the operating voltage and threshold voltage of a transistor decrease, it comes to be difficult to ignore a subthreshold current in the active state as well. Especially in a circuit block in which a large number of the same circuits are repeated as in driving circuits of word drivers, decoders and sense amplifiers and a small number of them are selected to operate, a subthreshold current continues to flow in a large number of non-selected circuits. A method to solve this problem is described in Very Large Scale Integration Memory, (1994), Baifukan, p. 367. FIG. 43 is a block diagram showing one example of the method. According to the method, a circuit is divided into a plurality of blocks BKi (i=1xe2x88x92n), and switch transistors PSWi are provided between sub power supply lines subVcci for respective blocks BKi and main power supply line Mvcc. Only switch transistor PSWm corresponding to a selected block BKm is turned on and other switch transistors PSWi are turned off to decrease a subthreshold current flowing in non-selected blocks.
Problem with Prior Art 1
In the circuit of the NOEMI configuration, N channel MOS transistor Qn2 is always in the on state as shown in FIG. 40. When the threshold of N channel MOS transistor Qn1 is decreased, the subthreshold current flowing between output node OUT and ground node GND in the standby state thus increases.
Problem with Prior Art 2
In practice, the subtrheshold current is substantially varied by variation in the threshold of a transistor caused when manufactured. Since the level of the minus voltage applied to the gate of N channel MOS transistor Qn11 is constant, the variation in the transistor threshold prevents the subthreshold current from efficiently being decreased, lowers the operating speed of the circuit even when the subthreshold current can be decreased, and so on.
Problem with Prior Art 3
In the circuit having hierarchical power supply lines and ground lines, the capacitance of the sub power supply line and the sub ground line increases. As a result, the sub power supply line and the sub ground line do not always have a power supply potential or a ground potential immediately after a power supply is turned on or immediately after a transition from the standby state to the active state. Accordingly, there caused problems such as a malfunction due to a timing mismatch and consumption of a peak current.
Problem with Prior Art 4
The circuit structure as shown in FIG. 43 requires substantial time from block selection to sufficient precharging of a sub power supply line in the block. The internal circuit in a selected block may operate even when its sub power supply line is not sufficiently precharged. Accordingly, there caused problems such as an access time delay and a malfunction.
An object of the present invention is to provide a semiconductor circuit device suppressing the effect of hot carriers in an active state and decreasing a subthreshold current in a standby state.
Another object of the present invention is to provide a semiconductor circuit device decreasing a subthreshold current regardless of variation in a transistor threshold.
Still another object of the present invention is to provide a semiconductor circuit device properly operating even immediately after a power supply is turned on or immediately after a transition from a standby state to an active state.
Yet another object of the present invention is to provide a semiconductor circuit device in which an internal circuit in a block properly operates immediately after the block is selected.
A semiconductor circuit device according to one aspect of the present invention has active and standby states and includes a logic circuit. The logic circuit includes an output node and first to third transistors. The first transistor is connected between the output node and a first power supply node, turned on/off in response to an input signal in the active state, and turned off in the standby state. The second transistor is connected between the output node and a second power supply node, and turned on/off complementarily to the first transistor in response to the input signal in the active state. The third transistor is connected between the output node and the first transistor, turned at least on when the first transistor is turned on in the active state, and turned off in the standby state.
In the semiconductor circuit device, the third transistor is turned at least on when the first transistor is turned on in the active state. Accordingly, the logic circuit operates in a similar manner to the case when the third transistor is not provided. Since the drain voltage of the first transistor is limited to (gate voltage of the first transistor)xe2x88x92(threshold of the first transistor), the effect of hot carriers can be suppressed. Meanwhile, the first and third transistors are off in the standby state. Therefore, a subthreshold current flowing between the output node and the first power supply node is decreased.
Preferably, at least one of the first and third transistors has a threshold higher than the threshold of the second transistor. In the semiconductor circuit device, therefore, the subthreshold current flowing between the output node and the first power supply node can further be decreased.
Preferably, the input signal is supplied to the gate of the third transistor.
In the semiconductor circuit device, the third transistor is turned at least on when the first transistor is turned on in response to the input signal in the active state, and turned off in the standby state. Accordingly, means for controlling on/off of the third transistor does not need to be provided separately.
A semiconductor circuit device according another aspect of the present invention has active and standby states, and includes a control signal generating circuit, an adjusting circuit and a logic circuit. The control signal generating circuit generates a control signal that is at a logic high level in the active state and at a level lower than a logic low level in the standby state. The adjusting circuit adjusts the low level of the control signal at a desired level. The logic circuit includes an output node, a first N channel MOS transistor, a P channel MOS transistor and a second N channel MOS transistor. The first N channel MOS transistor is connected between the output node and a ground node, turned on/off in response to an input signal in the active state, and turned off in the standby state. P channel MOS transistor is connected between the output node and a power supply node, turned on/off in response to the input signal in the active state, and turned on in the standby state. The second N channel MOS transistor is connected in series with the first N channel MOS transistor between the output node and the ground node, turned on in response to the control signal in the active state, and turned off in the standby state.
In the semiconductor circuit device, the first and second N channel MOS transistors are turned off in the standby state. At this time, the second N channel MOS transistor is turned strongly off in response to the control signal having a level lower than the logic low level. Accordingly, a subthreshold current flowing between the output node and the ground node is decreased. Further, the low level of the control signal received by the second N channel MOS transistor is adjusted at a desired level by the adjusting circuit. Accordingly, the subthreshold current flowing between the output node and the ground node can more efficiently be decreased.
A semiconductor circuit device according to still another aspect of the present invention has active and standby states, and includes a control signal generating circuit, an adjusting circuit and a logic circuit. The control signal generating circuit generates a control signal that is at a logic low level in the active state and at a level higher than a logic high level in the standby state. The adjusting circuit adjusts the high level of the control signal at a desired level. The logic circuit includes an output node, a first P channel MOS transistor, an N channel MOS transistor and a second P channel MOS transistor. The first P channel MOS transistor is connected between the output node and a power supply node, turned on/off in response to an input signal in the active state, and turned off in the standby state. The N channel MOS transistor is connected between the output node and a ground node, turned on/off in response to the input signal in the active state, and turned on in the standby state. The second P channel MOS transistor is connected in series with the first P channel MOS transistor between the output node and the power supply node, turned on in response to the control signal in the active state, and turned off in the standby state.
In the semiconductor circuit device, the first and second P channel MOS transistors are turned off in the standby state. At this time, the second P channel MOS transistor is turned strongly off in response to the control signal having a level higher than the logic high level. Accordingly, a subthreshold current flowing between the output node and the power supply node is decreased. Further, the high level of the control signal received by the second P channel MOS transistor is adjusted at a desired level by the adjusting circuit. Accordingly, the subthreshold current flowing between the output node and the power supply node can more efficiently be decreased.
Preferably, the adjusting circuit includes a charge pump circuit and a detecting circuit. The detecting circuit has an adjustable detecting level. The detecting circuit compares the output voltage of the charge pump circuit with the detecting level, activates the charge pump circuit when the output voltage has not reached the detecting level, and inactivates the charge pump circuit when the output voltage has reached the detecting level.
In the semiconductor circuit device, the output voltage of the charge pump circuit is made equal to the detecting level set at a desired value. Accordingly, the level of the control signal in the standby state can be adjusted at a desired value and the value can be kept constant.
A semiconductor circuit device according to yet another aspect of the present invention has active and standby states, and includes a main power supply line, a sub power supply line, a first adjusting circuit, a main ground line, a sub ground line, a second adjusting circuit, a plurality of first logic circuits and a plurality of second logic circuits. The first adjusting circuit receives a power supply voltage from the main power supply line, supplies the sub power supply line with the power supply voltage in the active state, and supplies the sub power supply line with an adjustable voltage lower than the power supply voltage in the standby state. The second adjusting circuit receives a ground voltage from the main ground line, supplies the sub ground line with the ground voltage in the active state, and supplies the sub ground line with an adjustable voltage higher than the ground voltage in the standby state. The plurality of first logic circuits each have a power supply node connected to the main power supply line and a ground node connected to the sub ground line and output a logic high level signal in the standby state. The second logic circuits each have a power supply node connected to the sub power supply line and a ground node connected to the main ground line and output a logic low level signal in the standby state.
In the semiconductor circuit device, the sub power supply line has a voltage lower than the power supply voltage and the sub ground line has a voltage higher than the ground voltage in the standby state. Accordingly, a subthreshold current flowing between the output nodes of the plurality of first logic circuits and the sub ground line as well as between the output nodes of the plurality of second logic circuits and the sub power supply line is decreased. The voltage levels of the sub power supply line and sub ground line at this time are adjusted at desired values by the first and second adjusting circuits, respectively. Accordingly, the subthreshold current can more efficiently be decreased.
A semiconductor circuit device according to yet another aspect of the present invention has active and standby states, and includes a main power supply line, a sub power supply line, a first switching element, a main ground line, a sub ground line, a second switching element, a plurality of first logic circuits and a plurality of second logic circuits. The first switching element is connected between the main power supply line and the sub power supply line, turned on when a power supply is turned on and in the active state, and turned off in the standby state. The second switching element is connected between the main ground line and the sub ground line, turned on when a power supply is turned on and in the active state, and turned off in the standby state. The plurality of first logic circuits each have a power supply node connected to the main power supply line and a ground node connected to the sub ground line and output a logic high level signal in the standby state. The plurality of the second logic circuits each have a power supply node connected to the sub power supply line and a ground node connected to the main ground line and output a logic low level signal in the standby state.
In the semiconductor circuit device, when a power supply is turned on and in the active state, the first and second switching elements are turned on and the sub power supply line and the sub ground line are precharged to power supply and ground potentials, respectively.
Preferably, the semiconductor circuit device further includes a latch circuit and a logic controlling circuit. The logic controlling circuit passes the output signal of the latch circuit in the active state and supplies the logic circuit with a signal, as an input signal, for turning off the first transistor regardless of the output signal of the latch circuit in the standby state.
In the semiconductor circuit device, the first transistor included in the logic circuit is turned on/off in response to the output signal of the latch circuit in the active state and turned off in the standby state. Accordingly, there is no need to consider the level of the input signal to the logic circuit in the standby state.
A semiconductor circuit device according to yet another aspect of the present invention includes a main power supply line, n blocks, a block selecting circuit, n switching elements and a controlling circuit. The n blocks each have a sub power supply line and an internal circuit connected to the sub power supply line. The block selecting circuit selectively activates the n blocks. The n switching elements are each connected between the main power supply line and the sub power supply line in a corresponding block. The controlling circuit turns on each of the m switching elements, of the n switching elements, which include a switching element corresponding to a block to be activated by the block selecting circuit and thereafter turns off a switching element corresponding to a block other than the block to be activated by the block selecting circuit. Preferably, m is n or less.
In the semiconductor circuit device, each of the m switching elements which include a switching element corresponding to a block to be activated by the block selecting circuit is turned on, and all sub power supply lines included in the blocks corresponding to the m switching elements are precharged to the power supply voltage. Thereafter, a switching element corresponding to a block other than the block to be activated by the block selecting circuit are turned off. As a result, when a block to be activated by the block selecting circuit is activated, the sub power supply line in the block has sufficiently be precharged. Accordingly, the internal circuit in the block will not cause a malfunction.
A semiconductor circuit device according to yet another aspect of the present invention includes a main power supply line, n blocks, a block selecting circuit, n first switching elements, a first controlling circuit, n second switching elements and a second controlling circuit. The n blocks each have a sub power supply line and an internal circuit connected to the sub power supply line. The block selecting circuit selectively activates the n blocks. The n first switching elements are each connected between the main power supply line and the sub power supply line in a corresponding block. The first controlling circuit turns on a first switching element corresponding to a block to be activated by the block selecting circuit. The n second switching elements are each connected in parallel with a corresponding first switching element. Before the block selecting circuit activates a block, the second controlling circuit turns on each one of the m second switching elements, of the n second switching elements, which include a second switching element corresponding to a block to be activated by the block selecting circuit. Preferably, m is n or less.
In the semiconductor circuit device, each one of the m second switching elements, of the n second switching elements, which include a second switching element corresponding to a block to be activated by the block selecting circuit is turned on before the block selecting circuit activates a block, and all sub power supply lines included in blocks corresponding to the m second switching elements are precharged to the power supply voltage. Thereafter, a first switching element corresponding to a block to be activated by the block selecting circuit is turned on. As a result, when a block to be activated by the block selecting circuit is activated, the sub power supply line in the block has sufficiently be precharged. Accordingly, an internal circuit in the block will not cause a malfunction.
A semiconductor circuit device according to still another aspect of the present invention includes a main power supply line, a plurality of blocks, a block selecting circuit, a plurality of switching elements and a controlling circuit. The plurality of blocks each have a sub power supply line and an internal circuit connected to the sub power supply line. The block selecting circuit selectively activates the plurality of blocks. The plurality of switching elements are provided corresponding to the plurality of blocks and each connected between the main power supply line and a corresponding block. The controlling circuit successively turns on the plurality of switching elements before the block selecting circuit activates a block.
In the semiconductor circuit device, a plurality of switching elements are successively turned on and the sub power supply lines included in corresponding blocks are precharged to the power supply potential before the block selecting circuit activates a block. Accordingly, the sub power supply lines in all blocks can be precharged without causing a peak current that is produced when the sub power supply lines in all blocks are precharged simultaneously.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.